Advanced Packaging Technology: The Core Engine Empowering Future Chip Development

3DPackaging technology

fromIn the fields of aviation, aerospace, and computer science, electronic devices and systems have a significant impact on small businessesWith the continuous improvement of high-density assembly requirements such as standardization, lightweighting, and thinningMCMOn the basis of two-dimensional assembly, for a limited area, electronic assembly must inevitably move towards two-dimensional assemblyzDirection development, this is what we callthree-dimensional(3D)Encapsulation technology is an effective means of achieving system assembly for a considerable period of time in the future.

implement3DencapsulationThere are mainly three methods. One is the buried type, which means that the components are buried on the substrateMulti layer wiringInternally embedded or fabricated within the substrate. Resistors and capacitors can generally be buried in multi-layer substrates using thick or thin film methods along with multi-layer wiringICChips generally need to be tightly attached to the substrate. You can also make slots on the substrate first, and thenICChip embedding, usingepoxy resinAfter fixing, align with the substrate plane, then implement multi-layer wiring, and install the top layer againICChip, thus achieving3DEncapsulation. The second method isactiveSubstrate type, this is made of siliconwaferIC(WSI)When making a substrate, firstWSIUsing general semiconductorsICThe production method involves the integration of one-dimensional devices, which becomes an active substrate. Then implement multi-layer wiring, with various other installations still installed on the top layerlCChips or other components, to achieve3DEncapsulation. This method is one that people ultimately pursue and strive to achieve3DPackaging technology. The third method islaminationMethod, which involves placing two or more bare chips or packaged chips in the vertical chip directioninterconnectBecoming Simple3DEncapsulation. More often than not, it involves assembling items that have already been single-sided or double-sidedMCMStacked together and interconnected in multiple layers, it can be achieved3DEncapsulation. It can be heated and sunk both above and below, this3DStructure, also known as3D．MCMDue to3DThe assembly density is high, the power consumption is high, and the substrate is mostly a high thermal conductivity substrate with good thermal conductivity, such as siliconaluminum nitrideandDiamond filmWait. Multiple silicon wafers can also be stacked together to form3DEncapsulation.

Advanced stacked structure3DPackaging technology

In recent years, advanced packaging technologies have emergedICThe manufacturing industry is beginning to emerge, such asMulti chip module（MCM）It means to combine multipleICChips are packaged according to functional combinations, especially in three-dimensional form（3D）Packaging first breaks through the concept of traditional planar packaging, with assembly efficiency reaching up to200%The above. It enables multiple chips to be stacked within a single package, achievingstorage capacityThe doubling of, known as layered in the industry3DEncapsulation; Secondly, it directly interconnects the chips, significantly reducing the length of the interconnects, resulting in faster signal transmission and less interference; Furthermore, it will have multiple differencesFunctional chipStacking together enables a single package to achieve more functions, thus forming a new concept for system chip packaging; Finally, adopt3DThe packaged chip also has advantages such as low power consumption and fast speed, which makesElectronic information productsReduce the size and weight by ten times. just because3DEncapsulation has unparalleled capabilitiestechnical advantagePlus multimedia andWireless communication equipmentThe demand for its use has given this new packaging method broad development space.

The most common bare chip stack3DThe packaging first involves flipping and soldering qualified chips with growth bumps onto a thin film substrate made of ceramic or epoxy glass, which has conductive wiring and internal interconnect solder joints, as well as external interconnect solder joints on both sides. Then, multiple thin film substrates are stacked and interconnected.

Bare chip stackprocessTo: The first step is to grow bumps on the chip and perform reverse soldering. If gold convex points are used, thengolden silkpelletizingThe method of forming convex points, intwo hundred and fifty～400 ℃Apply pressure to interconnect the chip with the substrate; If lead tin bumps are used, then use Pb95Sn5Convex points with a weight ratio that have a higher melting point and do not melt during the next process. The specific method is to first set the temperature below the melting point of the convex point（one hundred and eighty～250 ℃）At this temperature, the chip and substrate are soldered by metal diffusion; Then heat it up totwo hundred and fifty～400 ℃At this temperaturesolderThe ball melts and the welding is completed. The temperature of the first step is obtained through yield testing, and when it is lower than150 ℃The phenomenon of intermittent circuit breaking has increased; And when higher than300 ℃When, the adjacent solder jointsShort circuit phenomenonIncrease. Step 2, between the chip and the substrate0.05 mmFill in the gapsepoxy resin adhesiveThat is, proceed with filling. Step three, stack the substrates with raised bumps together, where the bumps on the substrate are solder bumps composed ofPb/SnorSn/AgThe melting point is set attwo hundred～240 ℃The final step is to stack the substrates and thentwo hundred and thirty～250 ℃Welding is carried out at a certain temperature.

MCMThe process flow of stacking is basically the same as that of bare chip stacking. In addition to the interconnection method used for welding the edge conductors mentioned above, the stacked layer3DThere are various interconnection methods for packaging, such asWire bondingStacked chips are a type of chip that uses lead wiresbondingThe application scope of this method is relatively wide for achieving stacked interconnection through technology. In addition, the stacked interconnect process also includes stacked layerscarrier tapeFoldingFlexible CircuitWait for the way. Stacked carrier tape is automatically bonded using carrier tape（TAB）ImplementICInterconnection can be further divided into printed circuit boards（PCB）StackingTABandLead frame TABThe folding flexible circuit method is to first install bare chips on flexible materials, and then fold them to form a three-dimensional stacked packaging form.

Advanced packaging refers to a new technological system that uses innovative processes such as flip chip, bumping, wafer level packaging (WLP), 2.5D/3D integration, etc. to achieve higher density interconnection, shorter signal paths, and heterogeneous integration at the packaging level. Compared with traditional packaging, its core advantage lies in improving interconnect efficiency, significantly shortening the communication distance between chips, reducing signal delay and power consumption through technologies such as through silicon vias (TSV), rewiring layers (RDL), and micro bumps. For example, TSV technology shortens the signal transmission distance of different chip layers from millimeter level to micrometer level through vertical interconnection, and the transmission speed can be increased by several times. Realize system level integration: Integrate multiple chiplets with different process nodes and functional types into a single package to achieve "system level packaging" (SiP). This modular design of building blocks not only breaks the bottleneck of single-chip performance, but also allows chips from different suppliers to work together, accelerating product iteration. Optimizing cost and design flexibility: Traditional SoC (System on Chip) designs require the integration of all functions at the same process node, resulting in long development cycles and high risks. Advanced packaging technology allows for the decomposition of chips into multiple functional modules, each produced using the most suitable process, and ultimately packaged and integrated, significantly reducing overall research and development costs and chip risks, and shortening product time to market. In addition, advanced packaging technology has also driven innovation in packaging materials and processes, such as the application of low-temperature bonding, hybrid bonding, and other processes, further improving packaging yield and reliability. These technological breakthroughs have upgraded packaging from a simple "protection and connection" function to a key engine for optimizing chip performance.